1. Overflow

in 2’s complement calculation occurs when the result exceeds the max number

possible in that form. The result of an overflow could be severe. When adding

two positive numbers, if overflow happens, the result would be a negative

number. This is because when overflow occurs the sign bit would be set. With

the sign bit set, the number would represent a negative quantity.

Given below is an example which showcases this for a 3-bit system where bit 2

represents the sign bit:

A = 3 (011)

B = 2 (010)

The result for A+B as we know would be = 5

Using 2’s complement arithmetic:

011 + 010 = 101

The above number in 2’s complement form represents: -3

2. The

two’s complement follows the following for an X-bit wide system:

The most significant bit (MSB) forms the sign-bit. Thus, the user knows for

every calculation that the MSB significant bit would give us the sign. This

makes it easy to get the sign of the number. It also solves the problem of

representing the negative numbers easily, with the MSB helping us to identify

whether the number is positive or negative.

Apart from the explicit sign bit, the magnitude can also be easily computed for

both positive (sign bit 0) and negative numbers (sign bit 1). The magnitude for

the positive number could be directly computed using the value the number

represent. For negative numbers, we would need to use the two’s complement

rules and then calculating the magnitude. In this way both negative and

positive numbers can be represented and calculated easily.

3. Given

8-bit numbers:

a. 121

– Since it is a positive number and within the range of an 8-bit system. The

binary representation would itself give the 2’s complement:

121

= 0111 1001

b. -53

– For negative number we would need to follow the 2’s complement arithmetic

rules:

i. Represent

53 in binary: 0011 0101

ii. Negate

the result discarding the sign bit: 100 1010

iii. Add

1 to the result and add the sign bit: 1100 1011

-53

= 1100 1011

4. Given

8-bit numbers:

a. 1101

1001 – Since it is a negative number we would need to use 2’s complement arithmetic

to get the exact value:

i. Negate

the number discarding the sign bit: 010 0110

ii. Add

1 to the result and calculate the magnitude: 010 0111 = -39

1101 1001 = -39

b. 0110

0010 – For positive number we could get the magnitude directly:

0110

0010 = 98

5. The

IEEE-754 Single Precision Floating point representation is shown below:

The IEEE-754 single precision floating point format

uses 32-bits to represent the floating point number. The bits are divided as

shown in the figure above:

Bits 22:0 – Form the Mantissa (or the

Fraction part)

Bits 30:23 – Form the Exponent part

Bit 31 – Forms the sign bit

Using the above bit positions, we can represent a

floating-point number easily. Given below is the way, how a floating-point

quantity could be expressed. This is how the floating point number is

expressed:

(-1)S

x 1.F x 2(E-127)

Here:

S: Represents the Sign bit

F: Magnitude of the fraction part

E: Magnitude of the exponent part

Using the above information, we can express floating

point numbers easily. All the three different quantities can be calculated

separately and then the above equation can be used to get the actual value of

the floating-point number.

6. The

following shows the calculation for 56.25 using single precision floating point

numbers. It follows the same rules discussed in the previous answers relating

to the floating-point numbers:

56.25:

The binary expansion of the above number can be

calculated using the equation mentioned above. The three quantities are shown

below:

Sign bit = 0

Fraction = 11000010000000000000000

Exponent = 10000100

7. The

adder can be used to do both addition and subtraction using two’s complement

form. This is true because subtraction in 2’s complement form is nothing but

adding a number A with the 2’s complement version of the other number B.

The full-adder can be used as a

subtractor this depending on the following two inputs used with a controlled

inverter:

Carry in = 1 (The carry-in should be set)

B = ~B (Using the controlled inverter)

Here is the diagram which shows the

same:

Simple 4-bit adder:

Using the adder as a subtractor by

setting the Cin bit and negating B

8. a)

Characteristic and excitation table for T flip-flop:

Q(next)

= TQ’ + T’Q

Excitation Table:

Q

Q(next)

T

0

0

0

0

1

1

1

0

1

1

1

0

b) Characteristic and excitation table for J-K

flip-flop:

Q(next)

= JQ’ + K’Q

Q

Q(next)

J

K

0

0

0

X

0

1

1

X

1

0

X

1

1

1

X

0

9. Output

equation is shown below:

Y = (QA

+ QB) X

State equations are shown below:

QA(next)

= XQA + XQB

QB(next)

= XQB’

10. State

table and state diagram is shown below:

State Table:

Current State

(QAQB)

Input

(X)

Next State

(QA(next)QB(next))

00

0

00

00

1

01

01

0

00

01

1

10

10

0

00

10

1

11

11

0

00

11

1

10

State diagram is shown below:

State Mapping

(QAQB)

State Name

00

S0

01

S1

10

S2

11

S3